Alif Semiconductor /AE722F80F55D5AS_CM55_HP_View /ETH /ETH_MAC_MDIO_ADDRESS

RMII Busy The application sets this bit to instruct the MDIO to initiate a Read or Write access to the MDIO slave. The MAC clears this bit after the MDIO frame transfer is completed. Hence the software must not write or change any of the fields in ETH_MAC_MDIO_ADDRESS and ETH_MAC_MDIO_DATA registers as long as this bit is set. For write transfers, the application must first write 16-bit data in the ETH_MAC_MDIO_DATA[GD] field (and also ETH_MAC_MDIO_DATA[RA] field when the C45E bit is set) before setting this bit. When the C45E bit is set, it should also write into the ETH_MAC_MDIO_DATA[RA] field before initiating a read transfer. When a read transfer is completed (GB=0), the data read from the PHY register is valid in the ETH_MAC_MDIO_DATA[GD] field. Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect.

0 (Val_0x0): RMII busy is disabled

1 (Val_0x1): RMII busy is enabled

Clause 45 PHY Enable When this bit is set, Clause 45 capable PHY is connected to MDIO. When this bit is reset, Clause 22 capable PHY is connected to MDIO.

0 (Val_0x0): Clause 45 PHY is disabled

1 (Val_0x1): Clause 45 PHY is enabled

Operation Command 0 This is the lower bit of the operation command to the PHY. When in MDIO mode (MDIO master) this bit along with GOC_1 determines the operation to be performed to the PHY.

0 (Val_0x0): Operation command 0 is disabled

1 (Val_0x1): Operation command 0 is enabled

Operation Command 1 This is the higher bit of the operation command to the PHY. GOC_1 and GOC_O are encoded as follows: 0x0: Reserved 0x1: Write 0x2: Post read increment address for Clause 45 PHY 0x3: Read GOC_1 is encoded as follows: 0x0: Operation command 1 is disabled 0x1: Operation command 1 is enabled

Skip Address Packet When this bit is set, the MDIO does not send the address packets before read, write, or post-read increment address packets. This bit is valid only when the C45E bit is set.

0 (Val_0x0): Skip address packet is disabled

1 (Val_0x1): Skip address packet is enabled

CSR Clock (CLK_CSR) Range The CLK_CSR range selection determines the frequency of the MDC clock (ETH_MDC) according to the CLK_CSR frequency: The suggested range of CLK_CSR frequency applicable for each value (when Bit 11 = 0) ensures that the ETH_MDC is approximately between 1.0 MHz to 2.5 MHz freqency range. When Bit 11 is set, the user can achieve a higher frequency of the ETH_MDC than the frequency limit of 2.5 MHz (specified in the IEEE 802.3 Specification) and program a clock divider of lower value. For example, when CLK_CSR is of 100 MHz frequency and the user programs the CR field to 0xA, the resultant ETH_MDC is of 12.5 MHz which is above the range specified in IEEE 802.3 Specification. Program the following values only if the interfacing chips support faster MDC clocks:

0 (Val_0x0): CLK_CSR = 60-100 MHz; ETH_MDC = CLK_CSR / 42

1 (Val_0x1): CLK_CSR = 100-150 MHz; ETH_MDC = CLK_CSR / 62

2 (Val_0x2): CLK_CSR = 20-35 MHz; ETH_MDC = CLK_CSR / 16

3 (Val_0x3): CLK_CSR = 35-60 MHz; ETH_MDC = CLK_CSR / 26

4 (Val_0x4): CLK_CSR = 150-250 MHz; ETH_MDC = CLK_CSR / 102

5 (Val_0x5): CLK_CSR = 250-300 MHz; ETH_MDC = CLK_CSR / 124

6 (Val_0x6): CLK_CSR = 300-500 MHz; ETH_MDC = CLK_CSR / 204

7 (Val_0x7): CLK_CSR = 500-800 MHz; ETH_MDC = CLK_CSR / 324

8 (Val_0x8): CLK_CSR / 4

9 (Val_0x9): CLK_CSR / 6

10 (Val_0xA): CLK_CSR / 8

11 (Val_0xB): CLK_CSR / 10

12 (Val_0xC): CLK_CSR / 12

13 (Val_0xD): CLK_CSR / 14

14 (Val_0xE): CLK_CSR / 16

15 (Val_0xF): CLK_CSR / 18

Number of Trailing Clocks This field controls the number of trailing clock cycles generated on ETH_MDC after the end of transmission of MDIO frame. The valid values can be from 0 to 7. Programming the value to 0x3 indicates that there are additional three clock cycles on the ETH_MDC line after the end of MDIO frame transfer.

Register/Device Address These bits select the PHY register in selected Clause 22 PHY device. These bits select the Device (MMD) in selected Clause 45 capable PHY.

Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing. This field indicates which Clause 45 capable PHYs (out of 32 PHYs) the MAC is accessing.

Back to Back transactions When this bit is set and the NTC has value greater than 0, then the MAC informs the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted). The software can thus initiate the next command which is executed immediately irrespective of the number trailing clocks generated for the previous frame. When this bit is reset, then the read/write command completion (GB iscleared) only after the trailing clocks are generated. In this mode, it is ensured that the NTC is always generated after each frame. This bit must not be set when NTC=0.

0 (Val_0x0): Back to back transactions disabled

1 (Val_0x1): Back to back transactions enabled

Preamble Suppression Enable When this bit is set, the MDIO suppresses the 32-bit preamble and transmits MDIO frames with only 1 preamble bit. When this bit is 0, the MDIO frame always has 32 bits of preamble as definedin the IEEE specifications.

0 (Val_0x0): Preamble suppression disabled

1 (Val_0x1): Preamble suppression enabled